TS3124E

Model Vertical Resolution DSO Trigger Protocol Trigger (Decode) Electrical Validation TS3124E 8 bits I - - TS3124B 8 bits I, II I - TS3124H 8, 12-16 bits I, II I - TS3124V 8, 12-16 bits I, II I, II I2C, I3C, SPI, UART,... Datasheet [PDF]   DSO Trigger I ：Edge, Either, External, Falling, Rising, Video, Width DSO Trigger II ：Runt, Pattern/State, Timeout, Transition, Setup/Hold, B-Trigger, B-Event, Window Protocol Trigger/ Decode I：BiSS-C, CAN 2.0B/CAN FD, DALI, DP_Aux[1], MIPI I3C 1.1, USB PD 3, ... Protocol Trigger/ Decode II：SVI3[2], SVID[3] [1] Optional DP_Aux adapter needed.[2] Upon request by user who is approved by AMD. SVI3 Bus Trigger / Decode are supported ONLY by TS3124V.[3] Upon request by user who has signed CNDA with Intel. SVID Bus Trigger / Decode are supported ONLY by TS3124V.